Advanced integrated circuits, such as those contemplated for the 45 nm node, will require the use of extra low-k dielectric (electrically insulating) materials for the interlevel dielectric layer interconnecting two levels of wiring. Low-k materials having a constant of somewhat less than 3.9 (the value for silicon dioxide) have already entered commercial production. However, even lower dielectric constants, for example, below 2.5, will be required in the future. An example of this material is Black Diamond™ II (BDII) dielectric commercially available from Applied Materials of Santa Clara, Calif. This dielectric material, which Li describes in U.S. patent application Ser. No. 2003/0194495, may be characterized as carbon-doped silicon oxide (or silicon oxycarbide) having a carbon fraction of above 10 at %. Improvements include BDIIx dielectric, which is UV cured and may have a porosity of 30%, and DBIIebeam dielectric, which is cured with electrons. Other carbon-containing low-k dielectrics are known, including Silk® and Cyclotene® (benzocyclobutene) dielectric materials available from Dow Chemical. Many of these materials are characterized as organic or polymeric dielectrics.
A prototypical structure in the formation of an inter-level interconnect is illustrated in the cross-sectional view of FIG. 1. A lower dielectric layer 10 includes a conductive feature 12 formed at its surface. The conductive feature 12 for advanced inter-level connections is typically composed of copper but similar geometries apply to contacting active semiconductor regions of a silicon substrate. An upper dielectric layer 14 of ultra low-k dielectric material is deposited over the lower dielectric layer 10 and the conductive feature. A hole 16 is photolithographicafly defined and etched through the upper dielectric layer 14 to the conductive feature 14. For the typical dual damascene interconnect used in copper metallization, the hole 16 is composed of a narrow lower via forming the vertical interconnect to the conductive feature 12 and a wide upper trench forming the horizontal interconnect between different portions of the integrated circuit. For dual damascene structures, the conductive feature 12 may be part of the copper-filled trench formed in the lower level dielectric 10. After the hole has been etched, a thin substantially conformal barrier layer, for example, of Ta/TaN is coated, typically by magnetron sputtering onto the sides of the hole 16 as well as over the field area of the upper dielectric layer 14. A thin substantially conformal copper seed layer is then deposited over the barrier layer, typically also by magnetron sputtering. Thereafter, copper is electroplated into the hole 16 and over the field area. Finally, chemical mechanical polishing (CMP) is used to remove the copper outside the hole 16.
The photolithographic etching step, even after photoresist ashing, often leaves a carbonaceous or fluorocarbon polymeric layer 18 on the sides of the hole 16 which is advantageously used to achieve highly anisotropic etching but remains after cessation of etching. It also may leave an etching residue 20 at the bottom of the trench, which may be a combination of carbon, silicon and fluorine by products of the etching chemistry. Further, the exposed copper in the conductive feature 12 is likely to have oxidized to copper oxide. Yet further, ashing residue 22 tends to form at the lip of the hole 16. Etching residues 20 and copper oxide at the bottom of the hole 16, if not removed prior to barrier deposition before the metallization deposition, increase the contact resistance. The polymeric coating 18 and the ashing residues 22 interfere with the bonding of the barrier layer to the dielectric layer 14 so that the barrier layer and copper via structure may delaminate during fabrication or during operation, resulting in a substantial reliability problem. It is thus greatly desired to remove the residues 18, 20, 22 and the copper oxide before the barrier deposition begins.
With conventional silica dielectrics, it has been common to dry clean the wafer between the etching and deposition steps by sputter etching the patterned wafer to remove the residue. Such sputter etching typically involves highly energetic ions, which do not greatly affect silica dielectric layers, which are relatively hard. However, low-k dielectric layers tend to be relatively soft. Therefore, a sputter etch tends to deleteriously etch and degrade the low-k dielectric layer. A softer chemical etching may be performed using a oxygen plasma generated in the cleaning chamber adjacent the wafer, that is, an in situ plasma. This cleaning process proved satisfactory for the early forms of low-k dielectric having a dielectric constant k of about 3.7 and not being porous. However, the in situ oxygen plasma has proved unsatisfactory for the most recent ultra low-k films having a k value of about 2.5 and a porosity of greater than 10%. It is believed that the oxygen plasma includes a high fraction of oxygen atoms which are attracted to the negative self-bias that develops on a floating body exposed to the plasma. The oxygen ions then strike the ultra low-k film with sufficient energy to damage it. Accordingly, the practice has developed of cleaning the patterned wafer with an oxygen plasma generated from a remote plasma source (RPS), as disclosed by Wood et al. in U.S. Patent Application Publication 2004/0219789. The remotely generated plasma emphasizes electrically neutral radicals while the in situ plasma emphasizes electrically charged ions. The remotely generated oxygen plasma projects many neutral and low-energy oxygen radicals to the wafer, which oxidize and otherwise chemically react with the different residues to remove them.
However, excited oxygen has not proved satisfactory for the ultra low-k dielectric materials. The reduction in dielectric constant is often obtained by a high porosity in the dielectric material. Dielectric layers of BDII may have a porosity of over 10%, even above 30%. Therefore, they are not only very soft, they are also very reactive to an oxidizing dry cleaning. Furthermore, oxygen incorporated into the dielectric tends to produce a more polarizable bond than the silicon and carbon bonds, that is, to increase the dielectric constant. As a result, dry cleaning based on reducing chemistry has been developed using, for example, remotely generated plasmas of NH3 (see U.S. Pat. No. 6,440,864 to Kropewnicki et al.) or relatively high pressures of H2. The hydrogen approach has prevailed, but the results have still not been totally satisfactory. Even very small amounts of water vapor in the hydrogen plasma significantly reduce the hydrophobic property of the porous low-k film and thereby tends to increase the dielectric constant. Even pure hydrogen tends to increase the dielectric constant somewhat. Further, reasonable etching rates have been achieved by increasing the chamber pressure, but the capacity of power supplies need to follow the increased pressure. Also, at the higher hydrogen pressures, the fraction of the hydrogen from the remote plasma source that is ionized and leaks into the cleaning chamber is increased. Hydrogen ions tend to be energetically attracted to the wafer and we believed they damage the porous low-k material.